怎么写USB驱动，Cadence USB 2.0 Controller和PHY IP驱动移植

作者 将狼才鲸 日期 2022-03-26

本子文档所属的上级文档（Gitee仓库）： 才鲸 / 嵌入式知识图谱WiKi  

https://gitee.com/langcai1943/embedded-knowledge-wiki

一、写在前面  

• USB寄存器很复杂，USB协议栈很复杂，USB寄存器很多（几百个），USB驱动代码很多（几万行），想一个人从头到尾写出USB驱动是很困难的，最常用的方法是使用厂商的驱动源码进行移植和修改。
• 调试USB驱动时示波器的作用很小，因为D+ D-是差分高速信号。
• 调试USB驱动时先检查电源电压，最好是标准的5V，最差也要4.8~5.2V，电压不对时很多设备工作有误。
• 调试USB驱动时如果一开始就握手失败，可以用示波器量D+ D-信号，D+一开始是3.3V高，握手时降到1V，握手成功后D+ D-的信号都降到500mv，握手之后的通讯信号示波器就排不上用场了，只能用USB协议分析仪抓取数据分析。
• USB信号虽然是差分的，但当总线空闲期间两根线都是低电平，有数据来时另一根线才拉高一起出现差分信号；有时候你会看到只有一根线上有信号，那是一些特殊的状态切换，如复位、唤醒等。
• 如果板子上是外接的PHY芯片，那么不需要配置PHY相关的东西，只需要写控制器的驱动就可以了；如果PHY是集成到系统内部的，那么一般都需要配PHY的寄存器，比如时钟这些；PHY的寄存器一般都有默认值，有时候不配置PHY，PHY也能正常工作，但有时候需要手动修改一点寄存器值。

电脑USB电压是多少伏

• USB概述： USB基础知识概论1 USB基础知识概论2 接口与协议学习笔记-USB协议_USB2.0_USB3.0不同版本（三）
• 理论知识参考书籍： 《网络协议工程》《计算机网络》

二、USB寄存器举例  

• USB的协议很复杂，和网络驱动类似；调试时需要用到USB协议分析仪。
• USB硬件的寄存器很多，例如本模块就有0x88个硬件寄存器。
• USB模块中包含两部分：控制器和PHY
• Cadence USB模块介绍： Cadence USB 2.0 PHY Home: IP Portfolio > Design IP > Interface IP > USB IP > USB 2.0 PHY Cadence USB 2.0 Controller Home: IP Portfolio > Design IP > Interface IP > USB IP > USB 2.0 Controllers Cadence IP
• Candece的资料网上下不到，要通过供应商获取。
• USB模块中包含两部分：控制器和PHY，之间通过UTMI接口通信。 UTMI UTMI及USB 2.0 PHY高速传输特性分析 UTMI接口标准研究 USB学习之二 USB PHY
• 主芯片中USB硬件模块的寄存器： 系统配置寄存器中的USB中断、USB中断使能、时钟使能、复位比特 USB_CTRL_STATUS_ADDR USB_CLK_ADDR USB_CONFIG_ADDR USB_CTRL_BASE_ADDR USB寄存器基地址，后面跟着的寄存器非常多
• Cadence有提供USB驱动源码：

/**********************************************************************  * Copyright (C) 2014-2022 Cadence Design Systems, Inc.  * All rights reserved worldwide.  ***********************************************************************  * platform.c  * This platform depended code is example of initialization code  * for ZC702 Board with Cortex A9 that can be run under Xilinx SDK environment.  *  * This is only reference file and can vary depending on evnironment  * and platform used for running Core Driver and References code.  **********************************************************************/

可以参考的USB驱动1：STM32F4xx_HAL_Driver   可以参考的USB驱动2：Mentor Graphics uC/OS-II  

三、PHY寄存器详解  

• PHY主要配置UTMI的各种参数。
• UTMI：phy和controller之间的16pin数据pin和其它控制pin及协议，因为pin数较多一般用于芯片内部。
• UTMI资料： UTMI接口标准研究 USB、UTMI、ULPI UTMI及USB 2.0 PHY高速传输特性分析
• 需要设置的功能有：频率选择、复位、速度选择、

四、驱动编写  

• USB工作流程：
• USB工作流程依次是握手连接、控制枚举和数据传输。
• 设备检测：D+线被上拉到3.3V。随后在1v电平下D+和D-差分传输三个方波进行握手。握手完成后数据传输（复位、唤醒等）是以D+ D-电平在500mv进行。
• 进行高速握手、枚举、数据传输。
• 在握手完成后，真正的数据传输时，数据包都有一定的格式。写驱动不用关心这些格式，调试USB驱动时能用协议分析仪直接抓出来。
• 其实吧，USB不用自己写驱动！会移植芯片原厂的驱动Demo就可以啦！最主要的是把PLL时钟配置好，寄存器基地址偏移设置好，中断配置好，其实就齐活了。懂得了一点USB协议知识，会查握手信号，会使用USB协议分析仪查找通讯失败的地方就可以了。就是这么简单。

• 《Cadence USB2.0 PHY Specification》 一些时序和电气特性
• 《Cadence USB2.0 PHY User Guide》 芯片设计相关内容和寄存器介绍。 PHY macro diagnostic control register PHY macro diagnostic APB access address register PHY macro diagnostic APB access write data register PHY macro diagnostic APB access read data register PHY macro diagnostic APB access control register Register Name PLL_REG12 PLL_REG13 UNUSED_REG0 UNUSED_REG1 UNUSED_REG2 UNUSED_REG3 UTMI_REG_EX1 UTMI_REG_EX2 UTMI_REG_EX3 UTMI_REG_EX4 UTMI_REG_EX5 UTMI_REG0 UTMI_REG1 UTMI_REG7 UTMI_REG15 UTMI_REG19 UTMI_REG20 UTMI_REG29 UTMI_REG30 TX_REG2 TX_REG5 RX_REG0 CALIB_STAT_3 CALIB_STAT_4 CALIB_STAT_5 CALIB_STAT_6
• 控制器寄存器手册：《Cadence USB 2.0 High Speed Controller IP - CUSB2 Special Function Register Specification》

1 The Device and Host Special Function Registers ........................................ 18  

1.1 The OUT (HCIN) 0 endpoint byte count register (out0bc, hcin0bc)__ 18  

1.2 The IN (HCOUT) 0 endpoint byte count register (in0bc, hcout0bc)__ 18  

1.3 The 0 endpoint control/status register (ep0cs, hcep0cs)______ 19  

1.4 The LPM control low byte register (lpmctrll, hclpmctrll) ______ 21  

1.5 The LPM control high byte register (lpmctrlh, hclpmctrlh)_____ 22  

1.6 The LPM clock control (lpmclock)____________ 23  

1.7 The 0 endpoint fifo register (ep0fifo, hcep0fifo) ________ 23  

1.8 The OUT (HCIN) X endpoint byte count register (outxbc, hcinxbc)__ 24  

1.9 The OUT (HCIN) X endpoint control register (outxcon, hcinxcon) ___ 26  

1.10 The OUT (HCIN) X endpoint control and status register (outxcs, hcinxcs) 27  

1.11 The IN (HCOUT) X endpoint byte count register (inxbc, hcoutxbc)__ 29  

1.12 The IN (HCOUT) X endpoint control register (inxcon, hcoutxcon) ___ 31  

1.13 The IN (HCOUT) X endpoint control and status register (inxcs, hcoutxcs) 32  

1.14 The FIFO X data register (fifoxdat, hcfifoxdat) _________ 34  

1.15 The HC 0 endpoint control register (hcep0ctrl) _________ 35  

1.16 The HCOUT X endpoint error register (hcoutxerr) _______ 36  

1.17 The HCIN X endpoint error register (hcinxerr)__________ 37  

1.18 The HCOUT X endpoint control register (hcoutxctrl) _______ 39  

1.19 The HCIN X endpoint control register (hcinxctrl)________ 39  

1.20 The IN (HCOUT) 0 endpoint data buffer (ep0indat, hcep0outdat)_____ 40  

1.21 The OUT (HCIN) 0 endpoint data buffer (ep0outdat, hcep0indat)___ 40  

1.22 The setup data packet buffer (setupdat) __________ 41  

1.23 The IN (HCOUT) X endpoint interrupt request register (inxirq, hcoutxirq) 41  

1.24 The OUT (HCIN) X endpoint interrupt request register (outxirq, hcinxirq) 42  

1.25 The USB interrupt request register (usbirq, hcusbirq)________ 43  

1.26 The external interrupt request register (extirq)_________ 44  

1.27 The OUT X endpoint ping interrupt request register (outxpngirq) ___ 45  

1.28 The IN (HCOUT) X FIFO full interrupt request register (inxfullirq, hcoutxfullirq) 46  

1.29 The OUT (HCIN) X FIFO empty interrupt request register (outxemptirq,  hcinxemptirq) ___________________ 47  

1.30 The IN (HCOUT) X endpoint interrupt enables (inxien, hcoutxien) __ 48  

1.31 The OUT (HCIN) X endpoint interrupt enable register (outxien, hcinxien) 48  

1.32 The USB interrupt enable register (usbien, hcusbien) ________ 49  

1.33 The external interrupt enable register (extien) _________ 50  

1.34 The OUT x ping interrupt enable register (outxpngien) _______ 50  

1.35 The IN (HCOUT) x FIFO full interrupt enable register (inxfullien, hcoutxfullien) 51  

1.36 The OUT (HCIN) x FIFO empty interrupt enable register (outxemptien,  hcinxemptien) ___________________ 52  

1.37 The USB interrupt vector register (ivect, hcivect) _______ 53  

1.38 The FIFO interrupt vector register (fifoivect, hcfifoivect)______ 53  

1.39 The endpoint reset register (endprst, hcendprst) _______ 53  

1.40 The USB control and status register (usbcs, hcusbcs)________ 55  

1.41 The USB frame counter (frmnr) _____________ 56  

1.42 The Function Address register (fnaddr, hcfnaddr) _______ 57  

1.43 The Clock Gate register (clkgate, hcclkgate) _________ 57  

1.44 The FIFO control register (fifoctrl, hcfifoctrl) _________ 58  

1.45 The Speed Control register (speedctrl) ___________ 59  

1.46 The Sleep Clock Gate register (sleepclkgate) __________ 59  

1.47 The HC Port control register (hcportctrl) __________ 60  

1.48 The HC Frame number register (hcfrmnr) _________ 61  

1.49 The HC Frame remain register (hcfrmremain)__________ 62  

1.50 The HCIN X error interrupt request register (hcinxerrirq) _____ 63  

1.51 The HCOUT X error interrupt request register (hcoutxerrirq) ______ 64  

1.52 The HCIN X error interrupt enable register (hcinxerrien) _____ 64  

1.53 The HCOUT X error interrupt enable register (hcoutxerrien)_____ 65  

1.54 The Address Test Register (tr_addr) ___________ 65  

1.55 The Write Data Test Register (tr_wdata) __________ 66  

1.56 The Read Data Test Register (tr_rdata)___________ 66  

1.57 The Control Test Register (tr_ctrl)___________ 67  

1.58 The ISO auto-arm register (isoautoarm) __________ 67  

1.59 The ISO control register (isodctrl) ___________ 68  

1.60 The ISO auto dump enable register (isoautodump)______ 69  

1.61 The PHY control 2 register (phyctrl2)___________ 70  

1.62 The PHY control 1 register (phyctrl1)___________ 70  

1.63 The PHY control 0 register (phyctrl0)___________ 70  

1.64 The OUT (HCIN) 0 Max packet size (out0maxpck, hcin0maxpck) _____ 71  

1.65 The OUT (HCIN) X Max packet size (outxmaxpck, hcinxmaxpck) ___ 72  

1.66 The HCIN X timer value (hcinxtmrh, hcinxtmrl) ________ 73  

1.67 The HCIN X timer control/status (hcinxtmr) _________ 74  

1.68 The HCOUT X timer value (hcoutxtmrh, hcoutxtmrl)_______ 75  

1.69 The HCOUT X timer control/status (hcoutxtmr)_________ 76  

1.70 The OUT (HCIN) X Start address (outxstaddr, hcinxstaddr) _____ 77  

1.71 The IN (HCOUT) X Start address (inxstaddr, hcoutxstaddr) _____ 79  

1.72 The IN X endpoint interrupt mode register (inxirqmode, hcoutxirqmode)_ 80  

1.73 The OUT X endpoint interrupt mode register (outxirqmode, hcinxirqmode) _ 81  

1.74 The microprocessor control register (cpuctrl) ________ 82  

1.75 The microprocessor control register 2 (cpuctrl2)________ 83  

1.76 The RX debug byte count register (debug_rx_bc) _______ 83  

1.77 The RX debug status register (debug_rx_status) _______ 83  

1.78 The debug interrupt request register (debug_irq) _______ 84  

1.79 The TX debug byte count register (debug_tx_bc) _______ 85  

1.80 The TX debug status register (debug_tx_status)________ 85  

1.81 The debug interrupt enable register (debug_ien) _______ 85  

1.82 The PHY workarounds enable register (phywa_en) ______ 86  

1.83 The PHY workaround 1 counter register (wa1_cnt) ______ 87  

1.84 The OTG workaround register (otg_wa) __________ 87  

1.85 The ENDIAN SFR control/status register (endian_sfr_cs) _____ 87  

1.86 The ENDIAN SFR status register (endian_sfr_s) ________ 89  

1.87 The IN (HCOUT) X Max packet size (inxmaxpck, hcoutxmaxpck) ___ 90  

2 The OTG Controller Special Function Registers .......................................... 92  

2.1 The OTG interrupt request register (otgirq)________ 92  

2.2 The OTG FSM state register (otgstate) ___________ 92  

2.3 The OTG control register (otgctrl) ___________ 93  

2.4 The OTG status register (otgstatus) ___________ 94  

2.5 The OTG interrupt enable register (otgien) __________ 94  

2.6 The OTG ta_aidl_bdis time register (taaidlbdis) ________ 95  

2.7 The OTG ta_wait_bcon time register (tawaitbcon) ______ 96  

2.8 The OTG tb_vbus_pls time register (tbvbuspls) ________ 96  

2.9 The OTG force register (otgforce) ___________ 97  

2.10 The OTG tb_vbus_dischrg_pls time register (tbvbusdispls)____ 97  

3 The OTG2 Controller Special Function Registers ........................................ 98  

3.1 The OTG2 control register (otg2ctrl) ___________ 98  

3.2 The ADP/BC control register 0(adpbcctrl0) __________ 98  

3.3 The ADP/BC control register 1 (adpbcctrl1)________ 99  

3.4 The ADP/BC control register 2 (adpbcctrl2)________ 99  

3.5 The ADP/BC interrupt request register 1 (adpbc1irq) _______ 100  

3.6 The ADP/BC interrupt request register 2 (adpbc2irq) _______ 101  

3.7 The ADP/BC status register 0 (adpbc0status) _________ 101  

3.8 The ADP/BC status register 1 (adpbc1status) _________ 102  

3.9 The ADP/BC status register 2 (adpbc2status) _________ 102  

3.10 The ADP/BC interrupt enable register 1 (adpbc1ien)________ 103  

3.11 The ADP/BC interrupt enable register 2 (adpbc2ien)________ 103  

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