ARMv8 SMPEN设置详解：多核处理器配置

cpuectlr ---CPU Extended Control Register, EL1

   ------------Purpose Provides additional IMPLEMENTATION DEFINED configuration and control options for the processor.



多核使能 smpen BIT6
[6] SMPEN Enable hardware management of data coherency with other cores in the cluster. The possible values are:
0 Disables data coherency with other cores in the cluster. This is the reset value.
1 Enables data coherency with other cores in the cluster.
Note
Set the SMPEN bit before enabling the caches, even if there is only one core in the system.

[5:3] - Advanced SIMD and Floating-point retention control. The possible values are:
0b000 Disable the retention circuit. This is the reset value.
0b001 2 Architectural Timer ticks are required before retention entry.
0b010 8 Architectural Timer ticks are required before retention entry.
0b011 32 Architectural Timer ticks are required before retention entry.
0b100 64 Architectural Timer ticks are required before retention entry.
0b101 128 Architectural Timer ticks are required before retention entry.
0b110 256 Architectural Timer ticks are required before retention entry.
0b111 512 Architectural Timer ticks are required before retention entry.

[2:0] - CPU retention control. The possible values are:
0b000 Disable the retention circuit. This is the reset value.
0b001 2 Architectural Timer ticks are required before retention entry.
0b010 8 Architectural Timer ticks are required before retention entry.
0b011 32 Architectural Timer ticks are required before retention entry.
0b100 64 Architectural Timer ticks are required before retention entry.
0b101 128 Architectural Timer ticks are required before retention entry.
0b110 256 Architectural Timer ticks are required before retention entry.
0b111 512 Architectural Timer ticks are required before retention entry.

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